This invention relates to semiconductor patterning processes for printing features within a semiconductor material. Specifically, it relates to mechanisms for characterizing the transfer of design features into printed features.
A typical semiconductor product is formed from a number of features residing and coupled together within multiple semiconductor layers. Each layer will typically include numerous features belonging to the same or different devices. Each layer of features or pattern is generally formed using some type of semiconductor patterning process, such as photolithography. Each layer pattern is first formed in a photoresist material that is disposed over a particular semiconductor material. Exposure light is then passed through a mask, which forms a design pattern on the resist material, and this design pattern is then exposed onto the resist material forming an exposed pattern on the resist material. Subsequent development of the exposed resist pattern results in activation of such pattern so that the developed resist pattern can be used during an etching process to prevent the semiconductor material underlying the developed resist pattern from being etched away while the semiconductor material that is not underlying the developed resist pattern is etched away, or visa versa. Thus, the semiconductor material underlying the resist pattern areas (or the areas outside the resist pattern) is patterned to form product features.
Patterning processes (e.g., photolithography) are becoming very challenging as the feature sizes go below the standard resolution limit of the patterning tool. One challenge includes achieving an accurate transfer of the design features into final patterned features. Since the wavelength(s) used in the photolithographic process is often longer than the size of the features that are to be printed, this gives rise to various types of diffraction and “smearing” effects when the exposure light is passed through the mask, so that the resulting printed pattern does not look like the design pattern on the mask. Various techniques have been developed to address this problem. One common technique is referred to as Optical Proximity Correction (OPC). OPC applies systematic changes to the mask geometries to compensate for the nonlinear distortions caused by optical diffraction and resist process effects. Specifically, these distortions include line-width variations dependent on pattern density, which affect a device's speed of operation and line-end shortening which can break connections to contacts. Causes include reticle pattern fidelity, optical proximity effects, and diffusion and loading effects during resist and etch processing. A mask incorporating OPC is thus a system that negates undesirable distortion effects during pattern transfer.
There are two basic OPC types, rule-based OPC and model-based OPC. Rule-based OPC sets forth rules describing what results can be generated by various types of mask corrections. For example, one rule may dictate that nonprintable square features are to be added to each corner of a square shaped mask feature having a certain size specification so as to minimize corner rounding on the printed square feature. These rules were typically based on experience. Model-based OPC, which currently is the most common OPC type, is accomplished by performing optical modeling for a particular system and then doing an inverse analysis of the model to determine the optimal OPC for a particular feature on the mask.
Generating OPC models is a significant burden for semiconductor product manufacturers. Typically, an OPC model is used to determine an OPC feature for a given mask feature type and lithography process, and this OPC result must then be used to print an actual test wafer to determine whether the models resulted in the desired feature shape. The printed features are measured, and such measurements are then fed back into the model to then tune the model to achieve even better results for a given set of conditions. For instance, the model is tuned for the specific photolitohographic process of the semiconductor product fabrication, including the specific reticle write tool used, the mask used, the numerical aperture used, the sigma used, the illumination mode used, and so on. In a second tuning stage, the models need to be tuned to the actual specific devices. Often, this two stage tuning process requires many thousands of iterative measurements to be performed to achieve an optimum OPC for a given device feature and set of process conditions.
Typically, the measurements are carried out using a scanning electron microscopy (SEM) system. These measurements are commonly referred to as CD-SEM (Critical Dimension Scanning Electron Microscope) measurements. CD-SEM systems have special software for measuring the size of critical dimensions. However, SEM systems require a significant amount of time—often several hours—to load and seal the wafer into the vacuum and then to acquire the high resolution image using the SEM. Also, the CD-SEM measurements do not provide any clear indication of the exact degree of modification or tuning that is necessary for the OPC model. Thus, it is difficult to efficiently determine whether particular feature characteristics, such as shape or location fidelity, are within specification or are likely to fail using conventional inspection techniques. Furthermore, the SEM systems use electron beams, which may modify the structural characteristics of the feature under test, due to the ionizing effects of the electron beams. SEM systems are also typically relatively slow, which is a significant drawback, since typically several thousands of measurements are required for OPC model optimization. The current SEM measurement methods also require multiple discrete measurements for each “point” in the OPC multi-parameter space.